Probabilistically Analysable Real-Time Systems

Jaume Abella

Dr. Jaume Abella is a Senior Research Scientist in the group on Interaction between the Computer Architecture and the Operating System (CAOS) at BSC where he leads hard real-time reliability and ultra-low power activities. He worked for more than 4 years at the Intel Barcelona Research Center, where he was responsible for activities on hardware degradation and multi-level memory hierarchies and had an outstanding contribution to Intel’s IP portfolio (15 patents filed). He participated in the FP4 MHAOTEU project and currently participates actively in the hardware designs for the PROARTIS FP7 project. Jaume is also involved in two research projects with the ESA. Jaume has wide experience in reliability, memory hierarchy design, low power and compilers. He has co-authored more than 40 papers in top conferences and journals (17 of them on reliability) and holds several awards. He is co-advisor of five PhD students.